1. Field of the Invention
The present invention relates to the field of metal-oxide-semiconductor field-effect-transistor (MOSFET) devices, and more particularly to a shallow trench large-angle-tilt implanted drain (LATID) device and method of fabrication.
2. Description of the Prior Art
With the continual improvement of semiconductor integrated circuit fabrication techniques, the number of devices which can be packed onto a semiconductor chip has increased greatly, while the size of the individual devices has decreased markedly. In submicron sized transistors, hot electron injection into the gate of such transistors poses a serious reliability problem. Modified structures and fabrication processes have been proposed to overcome this problem in the attempt to design a high speed very large scale integration (VLSI) manufacturable submicron MOS transistor which exhibits resistance to hot electron degradation.
One such device is the lightly doped drain (LDD) transistor. Please refer to FIGS. 1A and 1B, for the purpose of better understanding, which illustrate in cross-sectional views the process steps for fabricating a prior art LDD transistor. As can be seen in FIG. 1A, a gate oxide layer 11 and a polysilicon gate layer 12 are formed on a P-type silicon substrate 10 in sequence, thereby forming a gate electrode. Then, N-type impurities, such as phosphorous ions, are implanted into the silicon substrate 10 by using the gate electrode as a mask, so as to form a pair of lightly doped N.sup.- source/drain regions 13. Please now refer to FIG. 1B, a pair of sidewall spacers 14 are formed on the sidewalls of the gate electrode. Different N-type impurity, such as arsenic ions, is implanted into the silicon substrate 10 by using the gate electrode and the sidewall spacers 14 as a mask, so as to form a pair of heavily doped N.sup.+ source/drain regions 15. Thus, completes the fabrication of a prior art LDD MOSFET. Such LDD structure increases the transistor's resistance to hot electron degradation by reducing the peak electric field of the source/drain regions. However, since the N.sup.- source/drain regions 13 are not located under the gate electrode, a trapped charge is formed during hot electron injecting into the sidewall spacers 14, which causes a threshold voltage shift and results in unsatisfactory device characteristics.
A large-angle-tilt implanted drain (LATID) transistor was proposed to decrease hot electron degradation as well as prevent hot electrons from being trapped into the sidewall spacers. Please refer to FIGS. 2A and 2B, for the purpose of better understanding, which illustrate in cross-sectional view the process steps of fabricating a LATID transistor. As can be seen in FIG. 2A, a gate electrode comprising a gate oxide layer 21 and a polysilicon gate layer 22 is formed on a P-type silicon substrate 20. A thin oxide layer 23 is then formed on the exposed surface of the silicon substrate 20 and the gate electrode. N-type impurities, such as phosphorous ions, are implanted with an angle of about 45 degrees into the silicon substrate 20 to form a pair of lightly doped N.sup.- source/drain regions 24. Please note that the N.sup.- source/drain regions 24 are extended to areas under the gate electrode. Next, please refer to FIG. 2B, a pair of sidewall spacers 25 are formed on the sidewalls of the gate electrode. Different N-type impurities, such as arsenic ions, are implanted with an angle of about 7 degrees into the silicon substrate 20 by using the gate electrode and the sidewall spacers 25 as a mask, so as to form a pair of heavily doped N.sup.+ source/drain regions 26. Thus, completes the fabrication of the LATID transistor. This transistor structure not only decreases hot electron injection into the sidewall spacers, but also eliminates the threshold voltage shift due to the N.sup.- lightly doped source/drain regions 24 that are located under the gate electrode. It is obvious that the LATID transistor displays better device characteristics than the prior art LDD transistor does. However, since the N.sup.- lightly doped source/drain regions 24 are located under the gate electrode, a parasitic capacitor is formed between the polysilicon gate layer 22 and the N.sup.- lightly doped source/drain regions 24. Therefore the device operation speed is reduced. In addition, hot electrons which cause the device degradation are still easily injected into the gate oxide layer 21 since the electric field near the gate oxide layer 21 is still relatively intense.
It is therefore an object of the present invention to provide a MOS transistor structure which is made to increase the resistance to hot electron degradation and improve the device speed by decreasing the gate to drain capacitance.
It is another object of the present invention to provide a method of fabricating a MOS transistor with a high resistance to hot electron degradation and a low gate-to-drain capacitance.